The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a nanosheet field-effect transistor and methods of forming a nanosheet field-effect transistor.
Device structures for a field-effect transistor generally include a body region, a source and a drain defined in the body region, and a gate electrode configured to switch carrier flow in a channel formed in the body region. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, carrier flow occurs in an inversion or depletion layer in the channel between the source and drain to produce a device output current. The body region and channel of a planar field-effect transistor are located beneath the top surface of a substrate on which the gate electrode is supported.
A fin-type field-effect transistor (FinFET) is a non-planar device structure that may be more densely packed in an integrated circuit than planar field-effect transistors. A FinFET may include a fin consisting of a solid unitary body of semiconductor material, heavily-doped source/drain regions formed in sections of the body, and a gate electrode that wraps about a channel located in the fin body between the source/drain regions. The arrangement between the gate structure and fin body improves control over the channel and reduces the leakage current when the FinFET is in its ‘Off’ state in comparison with planar transistors. This, in turn, enables the use of lower threshold voltages than in planar transistors, and results in improved performance and lowered power consumption.
Nanosheet field-effect transistors have been developed as an advanced type of FinFET that may permit additional increases in packing density. The body of a nanosheet field-effect transistor includes multiple nanosheet channel layers stacked in a three-dimensional array. Sections of a gate stack may surround all sides of the individual nanosheet channel layers in a gate-all-around arrangement. The nanosheet channel layers are initially arranged in a layer stack with sacrificial layers composed of a material (e.g., silicon-germanium) that can be etched selectively to the material (e.g., silicon) constituting the nanosheet channel layers. The sacrificial layers are etched using, for example, hydrochloric acid vapor and removed in order to release the nanosheet channel layers, and to provide gate regions for the formation of the gate stack.
Before the nanosheet channel layers are released, source and drain regions are epitaxially grown from the side surfaces of the semiconductor nanosheet layers. Inner spacers are situated between the side surfaces of the sacrificial layers and the epitaxial semiconductor material constituting the source/drain regions. The inner spacers, which are formed of a dielectric material, are structurally intended to isolate the source/drain regions from the gate region during the etching process that releases the nanosheet layers. However, conventional inner spacers may have an associated curvature and may be thinner in regions adjacent to the nanosheet layers. The curvature may arise from diffusion of germanium from the sacrificial layers into the nanosheet channel layers and resulting local variations in the etching rate when etching the cavities in which the dielectric spacers are subsequently formed. The result is that conventional curved inner spacers are prone to breech and leakage that allows the etchant used during nanosheet release to reach and etch the source/drain regions.